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IP
UNIVE was founded in 1998, as SoC design company
Started to buid Analog IP in 2000
IP Partner with Global Foundry, Silterra, Vanguard
Business-Analog Design IP
Analog Design IP=”Silicon Tailoring”
Process Experience
0.35um, 0.25um, 0.18um, 0.13um, 90nm, 65nm and 40nm CMOS
IP Portfolio
-High Speed Interface : USB 1.1, USB 2.0, USB 2.0 OTG
-Special I/O : SSTL, LVDS, HSTL, GTL, PECL, MIPI, HDMI
-Converter : Analog to Digital, Ditital to Analog
-Clock : PLL, DLL, De-skew PLL
-Power : Power On Reset, Voltage Reulator, DC/DC
-Audio D-Class Driver(BTL), Universal level shifter
-Others : 802.11B, Optical Transceiver, DMB-T, Optic Interface
Business-Design Service
SoC Design Services
system Level Design Support
Macro Cell build(Analog/Digital block)
Dedicated or special cell buid
RTL coding & Logic Synthesis
Place & Route & Custom Layout
Design Vertification
Other Design Services
Standard Cell Library and GPIO Library Design
Custom Memory Block Design
Analog Design Kit for Mised-Signal Design
Special ESD structure for RF Pad
Project Esperience-Ⅰ
Each engineer has an average of 12 years of product design experience
52 design projects completed so far, over 98% success at first prototype & Over 70% products went to mass
Process technology
40nm, 6-14 layer metal CMOS
65/90nm, 4-9 layer metal CMOS process
0.13/1.8um, 3-9 layer metal CMOS process
0.25/0.35um, 3-6 layer metal CMOS process
0.5/0.6/0.8um, 3-5 layer metal CMOS process with HV options
0.11/0.18/0.20um, 4-6 layer metal HV CMOS process
0.5/0.6um 3-5 layer metal 50V/100V/200V/600V BCD process
Project Experience –Ⅱ
Design Complexity
Up to 15M gates with mixed signal bocks
Mega Cells : RAM, ROM, 80C51, ARM7, ARM9, OAK, Teak-lite DSP, etc.
Design Speed : Up to 5GHz
Up to 22 different clock sources
Clock skew control : internal 10ps, intra 30ps
Chip size : 16mm x 16mm
Power Supply
1.0/1.1V/1.2V/1.8V/2.5V/3.3V,5V/9V, 12V/15V/21V/32V, 50V/100V/200V, 600V